In order to provide highly integrated dynamic random access memories (DRAMs), memory cells which utilize trench capacitors for storing data have been developed. One such memory cell is described in Nesbit et al., A 0. 6 .mu.m.sup.2 256 Mb Trench DRAM Cell with Self-Aligned BuriEd STrap (BEST), IEDM 93-627. As described in U.S. Pat. No. 5,618,751, a buried plate electrode may be provided within the semiconductor substrate in which the trench capacitors are formed. The buried plate electrode provides the capability of controlling the voltage on one plate of each of a plurality of capacitors, rather than controlling the voltage on the substrate. Altering the voltage on a plate of a plurality of capacitors during read or write operations can be used to increase operating margins. Further, by partitioning the buried plate electrode, the current required to alter the voltage thereon can be reduced. Independent control of the voltage of the buried plate electrode and the semiconductor substrate avoids interference between the capacitors of the memory and transistors in peripheral circuits (e.g., sense amplifiers, addressing circuits) also formed on the substrate. Still further, the buried plate electrode allows the voltage across the capacitor dielectric to be limited.
In a DRAM such as the DRAM in the above-identified Nesbit article, a buried plate electrode (or buried well) is constituted by N-type impurity regions (which are formed by outdiffusing impurities from the trenches) and an N-well band formed by implantation (which connects together the outdiffused impurity regions). The outdiffusion results by providing a dopant source layer on the sidewalls of the deep trenches, patterning the dopant source film using a resist which is recessed to a level within the trench which is below the surface of the semiconductor substrate, stripping the resist, and annealing to outdiffuse the impurities. While it is possible for the buried plate electrode to be formed by outdiffusing the impurities so that one continuous region is formed, thereby eliminating the need for the N-well band, such a process is very sensitive to defects. For example, if trenches are missing, a substrate leakage current can result. In addition, the lateral resistivity of the buried plate electrode can be reduced using the N-well band.
The implantation for the N-well band is conventionally performed prior to etching the deep trenches in which the storage node capacitors are formed. This is disadvantageous for the following reasons. The N-well band implantation is performed using a patterned thick resist film 150 formed on a semiconductor substrate 155 as a block mask as shown in FIG. 1(a). The subsequently formed deep trenches must be aligned to this implantation. However, since there is no surface pattern after the implant it is difficult to align the mask for forming the deep trenches to the implantation. In order to overcome this problem, a first mask (a so-called zero level (ZL) mask) may be utilized for providing alignment marks 175 at the corner of the chip as shown in FIG. 1(b). In this case, the implant mask and the deep trench mask are aligned using these alignment marks. While this overcomes the alignment problems, the process requires several masks in addition to the deep trench mask. These additional masks complicate the manufacturing process by requiring additional process steps. These additional steps also increase the overall processing time and costs.